A flash memory may be a memory device that stores data, and may be beneficial in that data (for example, stored information) may not be lost during an interruption of power to the device. In this respect, the flash memory may be referred to as a nonvolatile memory. In the area of nonvolatile memory, the flash memory may be different from Dynamic RAM (DRAM) and Static RAM (SRAM).
Based on cell-array architecture, a flash memory may be classified as a NOR-type structure, where cells may be arranged in parallel between a bit line and a ground, or may be classified as a NAND-type structure, where cells may be arranged in series therebetween.
A NOR-type flash memory having a parallel structure may be used for booting a mobile phone, since it enables a high-speed random access on its reading operation.
The NAND-type flash memory having a serial structure may have a low reading speed, but it may have a high writing speed. In this respect, the NAND-type flash memory may be appropriate for data storage and may also be useful for miniaturization.
Flash memory may also be classified into a stack gate type and a split gate type on the basis of a unit cell structure.
According to a type of a charge storage layer, a flash memory may be classified into a floating gate device and a silicon-oxide-nitride-oxide-silicon (SONOS) device. A floating gate device may include a floating gate, which may be formed of polysilicon and may be covered with an insulator. In this case, a charge may be injected into or discharged from the floating gate by a channel hot carrier injector or Fowler-Nordheim (F-N) tunneling, whereby data may be stored in and erased from the floating gate.
In a related art flash memory device, a tunneling oxide layer may be positioned below a floating electrode. As this flash memory device is scaled-down, a gate height and a conjunction depth, as well as a channel length, may decrease and a tunneling oxide layer may also decrease in thickness.
However, there may be a limitation on the extent to which the tunneling oxide layer may be reduced in thickness. This may be because a thickness of tunneling oxide layer, through which the charge may be moved to the floating electrode, cannot be decreased to the extent below 7 nm or 8 nm.
If the tunneling oxide layer is too thin, the charge stored in the floating electrode may be discharged to a channel, which may reduce the ability of the memory to maintain the data.
Also, the flash memory devices may be arranged on a plane. If the devices cannot be scaled-down and if fewer devices may be provided, a memory storage capacity may be lowered in that degree.
Research and studies have been performed with respect to a three-dimensional flash memory. A unit cell of a three-dimensional flash memory may have multi-bit storage capacity and may overcome problems of the related art flash memory.
FIG. 1 is a cross sectional view illustrating a three-dimensional flash memory cell according to the related art.
As shown in FIG. 1, source and drain patterns 102 may be formed by removing predetermined portions of semiconductor substrate 101. Source and drain patterns 102 may be maintained at predetermined intervals. Source and drain patterns 102 may be formed by an impurity-ion implantation.
Tunneling capping layer 103 of an insulation layer may be formed on a surface of source and drain patterns 102. First polysilicon layer 104, which may become a floating gate, may be formed on substrate 101 including tunneling capping layer 103 and source and drain patterns 102.
A photoresist (not shown) may be coated onto first polysilicon layer 104. A photoresist pattern (not shown) may be formed between the source and drain patterns by photolithography.
By using the photoresist pattern as an etch-stopping layer, first polysilicon layer 104 formed between source and drain patterns 102 may be etched at a fixed interval, and may form a polysilicon pattern.
A related art three-dimensional flash memory formed as described herein may obtain a high level of integration of memory cells and also may also improve a scaling-down property. However, as shown in FIG. 1, a width difference between ‘a’ and ‘b’ patterns may inevitably form in the polysilicon pattern etched by the photoresist pattern due to the misalignment. The width difference of polysilicon pattern may badly affect the flash memory cell in its alignment, and may lower the memory capacity.